(1) Field of the Invention
The present invention relates to a voltage generating circuit and a voltage generating device which have the function of increasing an input voltage, a semiconductor device using the same, and a driving method thereof.
(2) Description of the Related Art
LSIs, which are constructed by integrating many MIS transistors, have been increasingly miniaturized in recent years. Miniaturization of MIS transistors has been progressing in close accordance with a scaling law. Because of this trend, gate oxide films are becoming ultrathin. Therefore, to prevent an increased leakage current passing through the gate oxide films, and to maintain reliability, a lower supply voltage is required. For example, according to a design rule that specifies a minimum gate length of 0.13 μm, the gate oxide film thickness is as thin as 1.5 to 1.9 nm and the supply voltage is as low as 1.2 to 1.5 V. When the potential of the gate of an MIS transistor and that of the source are equal, the potential of the drain is made lower than that of the source by the threshold voltage, creating a threshold voltage loss. This may lead to a reduced signal logic amplitude, and thus lowered reliability.
Such lowered reliability can be effectively prevented by supplying a raised voltage. It is possible to prevent loss of threshold voltage by supplying a voltage higher than the supply voltage to the gate of an MIS transistor using a voltage raising means. However, power to one system is preferably supplied from a single power source, because it is inefficient to provide two or more independent sources. One prior art technique that solves this problem is a bootstrap circuit, which generates a raised voltage from the supply voltage.
FIG. 14 is a circuit diagram showing the structure of a bootstrap circuit in the prior art. This bootstrap circuit comprises a first MIS transistor 101, which is an n-channel MISFET having a gate to which an input signal Vin is applied from an input terminal 110, and a second MIS transistor 102, which is an n-channel MISFET connected between a power line N101, which supplies a supply voltage Vdd, and the drain of the first MIS transistor 101. The connected portion of the first MIS transistor 101 and second MIS transistor 102 forms a node N102 (the node connected to the drain of the first MIS transistor 101 and the source of the second MIS transistor). The node N102 is connected to an output terminal 111 for outputting an output voltage Vout. A third MIS transistor 103 is an n-channel MISFET disposed between the gate of the second MIS transistor 102 and the power line N101. A supply voltage Vdd is applied to the gate of the third MIS transistor 103. A bootstrap capacitor 104 is between the node N102 and the connected portion of the gate of the second MIS transistor 102 and the source of the third MIS transistor 103, namely the node N103. A load capacitor 105 is connected between the output terminal 111 and the ground. Thus, the capacitor 104 and third MIS transistor 103 are provided so that the gate of the second MIS transistor 102 is floating at a high voltage. This enables the gate voltage of the second MIS transistor 102 to be raised higher than the supply voltage. It also enables the voltage of the node N102, i.e., the output voltage Vout outputted from the output terminal 111, to be maintained at the supply voltage Vdd as described below.
FIG. 15 shows the change over time in the input voltage Vin, output voltage Vout, and the voltage Vbt of the connecting node N103. When the input voltage Vin is 5 V, the output voltage Vout is 0 V since the first MIS transistor 101 is on. At this time, the voltage Vbt of the connecting node N103 has the value (Vdd−Vt3) lowered from the supply voltage Vdd by the threshold voltage Vt3 of the third MIS transistor 103. Subsequently, when the input voltage Vin is reduced from 5 V to 0 V, the output voltage Vout is increased because the first MIS transistor 101 is turned off. As the output voltage Vout rises, the voltage Vbt of the connecting node N103 is also increased by the capacitor 104. When the voltage Vbt rises above (Vdd−Vt3), the third MIS transistor 103 is turned off, and the gate of the second MIS transistor 102 becomes floating. Finally, the voltage Vbt of the connecting node N103 rises to (2 Vdd−Vt3). Since a sufficiently high voltage is applied to the gate of the second MIS transistor 102, the output voltage Vout rises to the supply voltage Vdd (=5V) without loss by the threshold voltage.
However, in this bootstrap circuit in the prior art, the electric charge of the capacitor 104 is reduced by current leakage. Therefore, the circuit has the problem that it is difficult to keep the voltage of the connecting node N103 at a raised voltage higher than the supply voltage over a long period. Another problem of the circuit is that if the voltage Vbt becomes floating while the voltage Vbt of the connecting node N103 is rising, the voltage Vbt becomes unstable because of the influence of the parasitic capacitance and parasitic resistance which exist in each part of the second and third MIS transistors 102 and 103.